1. Technical Field
Embodiments of the present invention generally relate to DRAMs and, more specifically, to a DRAM cell sense amplifier.
2. Background
FIG. 1 shows a conventional example of a DRAM cell sense amplifier in a configuration with precharge to the ground. To simplify the representation, the actual memory cells have not been shown, and an example of a memory architecture of the type to which embodiments of the present invention applies will be described in relation with FIG. 2.
Amplifier 1 comprises, between two terminals 2 and 3 of application of power supply voltages, respectively Vdd and GND (possibly via a switch not shown), a P-channel MOS transistor MP1 and an amplification stage forming a flip-flop, formed of two parallel branches each comprising a P-channel MOS transistor MP2, respectively MP3, and an N-channel MOS transistor, respectively MN2 and MN3. The junctions 4 and 5 of the respective series associations of transistors MP2 and MN2, and of transistors MP3 and MN3, are connected to so-called true or direct and complementary bit lines TBL and CBL of the memory cell column of the array network to which amplifier 1 is assigned. Terminals 4 and 5 also define respectively direct and complementary output terminals of sense amplifier 1. The gates of transistors MP2 and MN2 are connected to point 5 while the gates of transistors MP3 and MN3 are connected to point 4.
At each read cycle, a single memory cell of the column connected to amplifier 1 is read from, said cell being addressed by selecting a so-called word line by means of a decoder, not shown.
FIG. 2 very schematically and partially shows an example of architecture of a DRAM of the type to which embodiments of the present invention applies. For simplification, a single amplifier 1 (SAi) has been shown. Amplifier 1 is used to read bit lines CBLi and TBLi to which are connected memory cells 10T(ij), 10T(i,j+1) on line TBLi and cells 10C(ij) and 10C(ij+1) on line CBLi. Each cell is formed of a selection transistor T and of a capacitor C between bit line CBLi or TBLi and a bias potential Vp. The respective gates of transistors T are connected to word lines WLj and WLj+1. In FIG. 2, cells 10C(ij) and 10T(ij+1) have been shown in dotted lines to illustrate the fact that, to read, for example, from cell 10T(ij) of line i and of row j, the amplifier SAi assigned to the lines of rank i performs the reading from line TBLi while line CBLi is used as a reference line.
To read from the cells of a DRAM, the bit lines need to be precharged at a given voltage.
A first category of DRAMs provides a precharge of the bit lines to half the supply voltage, Vdd/2.
A second category of DRAMs to which embodiments of the present invention more specifically applies provides a precharge of the bit lines to ground to make the reading faster.
In this case, for each bit line, at least one reference cell 20 is used. Each reference cell 20 is typically formed of a memory point formed of a transistor T and of a capacitor C between line CBLi or TBLi and voltage Vp. The gates of transistors T are respectively connected to selection lines RefWL1 and RefWL2. Further, the memory points of cells 20 are connected by a transistor T to a line 21 of application of a reference voltage Vref (for example, equal to Vdd/2) by being simultaneously controlled by a signal PREF of precharge of the reference cells.
An example of a DRAM using reference cells in a ground precharge configuration is described in article “Embedded DRAM design and architecture for the IBM 0.11-μm ASIC offering” by J. E. Barth, J R. et al., published in IBM J. RES. & DEV., vol. 46, No 6, November 2002.
The use of reference cells in DRAMS increases the bulk of these memories (4 reference cells are further necessary in case of twisted bit lines in the above-mentioned example).
Further, the use of reference cells requires control of additional transistors, which generates an undesirable consumption equivalent to the reading from four cells instead of one.
Another disadvantage is that this lengthens the read cycles due to the time required to balance the charges of the reference cells.
U.S. Pat. Nos. 5,526,314, 6,046,609 and 6,201,418 disclose sense amplifiers having parallel connected branches of transistors in series, in which junction points of the series associations are not connected to bit lines, the bit lines being connected to gates of additional transistors connected in parallel with transistors of the branches.